AMD Displays the First Ryzen 9 5950X3D V-Cache Prototype

AMD Displays the First Ryzen 9 5950X3D V-Cache Prototype

AMD’s Amit Mehra and Bill Alverson spoke with Gamers Nexus about the origins of AMD’s 3D-VCache technology and how it became available on the company’s mainstream Ryzen consumer desktop platform, which includes some of the Best CPUs for Gaming. The pair demonstrated prototypes of AMD’s first Ryzen 3D-VCache parts, including 12-core and 16-core variants with two CCD 3D-VCache designs, during their talk with Gamer Nexus’ Steve Burke.

AMD’s revelation demonstrates that the company was indeed considering delivering high-core count Ryzen 5000 machines with 3D-VCache technology, as many fans had speculated. It also reveals that AMD was not conceptually confined to creating an 8-core architecture alone, but had the physical production capabilities to create multi-CCD 12-core and 16-core Ryzen 5000X3D CPUs if desired.

AMD’s Amit Mehra claims that the desktop implementation of AMD’s 3D-VCache technology began by mistake. The initial version was intended solely for servers, with AMD initially testing 3D-VCache editions of its EPYC server CPUs.

Ryzen 7000-based Vivobook Go notebooks from ASUS are equipped with Zen 2
AMD Displays the First Ryzen 9 5950X3D V-Cache Prototype

AMD chose to investigate 3D-Vcache functionality on Ryzen in the first place due to an “accident” during the production of presumably prototype Epyc 3D-VCache chips in which 7 CCDs were left over in a batch that couldn’t be used in an EPYC chip — EPYC CPUs at the time required 8 CCDs.

Mehra and his colleagues repurposed the seven V-Cache-equipped dies for desktop use, creating different designs with 8, 12, and 16 core versions. This prompted AMD to investigate the capabilities of 3D-VCache in desktop applications and discover the outstanding gaming performance V-Cache provides, resulting in the Ryzen 7 5800X3D.

AMD demonstrated two fully functional high-core count Zen 3 X3D prototypes to Gamers Nexus, including a 16-core and 12-core model with 3D-VCache on both CCDs. The chips were completely functional within Windows and were seen on screen actively executing an AIDA64 stress test. Bill Alverson demonstrated the chip’s specifications in Task Manager, demonstrating the huge 192MB of L3 cache packed on both CPUs courtesy of the “dual 3D-VCache” implementation.

Alverson and Mehra did not reveal AMD’s exact reasons for not shipping 12-core and 16-core Ryzen 5000X3D CPUs, but they did highlight the disadvantages of 3D-VCache on Ryzen CPUs with two CCDs, because there is a significant latency penalty that occurs when two CCDs talk to each other through the Infinity Fabric, effectively nullifying any potential benefits of 3D-VCache when an application is utilizing both CCDs.

Obviously, AMD did not consider hybrid consumers who could want a high core count X3D CPU for work and pleasure at the time, but it was something they were thinking about and remedied with the release of its Ryzen 9 7950X3D and 7900X3D processors.