Researchers developed a New Silicon Chip for Stronger Hardware Security

Researchers developed a New Silicon Chip for Stronger Hardware Security

Researchers developed a New Silicon Chip ‘Fingerprint’ for Better Hardware Security at a low cost. Researchers at NUS (National University of Singapore) Electrical and Computer Engineering have developed new, self-healing and self-healing Physically Unclonable Functions (PUFs). PUFs use inherent, special microchips manufacturing variants that include digital signatures for applications that can authenticate and protect devices. This technology also helps deter illicit copying of electronics, chip forgery, and physical assaults. This boosts the level of hardware security even in low-end chips systems.

Novel PUF silicon fingerprinting technique achieves long-term stability using machine learning, eliminates conventional attack points via physical hiding, and reduces cost of chip design and testing drastically.

Traditionally, PUFs are incorporated in a variety of commercial chips that specifically differentiate one silicon chip from another by producing a hidden key, equivalent to a human fingerprint. Such security avoids pirated hardware, stolen chip, and physical attacks. The research team of the Department of Electrical and Computer Engineering at the NUS Faculty of Engineering brought Silicon Chip Fingerprinting to the next stage with two major improvements: first, allowing PUFs self-healing; and second, enabling them to self-heal.

Self-healing PUFs

Despite their impressive evolution over the last decade, current PUFs still suffer from minimal stability and occasionally inaccurate fingerprint recognition. Often built as stand-alone circuits, they provide hackers with simple physical chip attacks. Conventionally, uncertainty is countered by overdesign, such as the design of error-correcting codes marginalized in the worst case, which greatly raises both chip costs and usage. In addition, before progressing to commercialization, chips with unstable PUFs must first be detected and discarded by rigorous research on a very large variety of environmental factors, with further increasing costs.

In order to resolve the holes, the team of NUS engineers has implemented a novel adaptation strategy that uses on-chip sensors and machine learning algorithms to forecast and detect PUF instability. This technique intelligently changes the tunable degree of correction to the minimum required and generates a more reliable, consistent PUF performance. The innovative solution, in particular, takes usage down to the lowest possible and is capable of identifying anomalous environmental factors such as temperature, voltage, or noise that are regularly used by hackers in physical attacks. An added benefit is that the traditional testing burden and cost are dramatically reduced by narrowing down the test cases required. This eliminates overdesign and unnecessary design costs, as most of the testing effort can be delegated to the available on-chip sensing and intelligence throughout the device’s lifetime.

“Our solution uses on-chip sensing and machine learning to allow effective prediction, identification, and adaptive suppression of PUF instability events. The ability to self-cure without loss of stability over the lifespan of the chip guarantees the stable generation of hidden keys at the highest degree of protection while preventing the burden of constructing and checking in the worst case, even though the latter is, in turn, uncommon and impossible. This decreases total costs, reduces time on the market, and reduces device capacity to prolong the battery life,” said Professor Massimo Alioto, who leads the Green IC Community behind this advancement in hardware security.

Reducing the expense of chip design and testing is crucial to improving hardware security even in extremely low-cost and low-power silicon systems, such as the Internet of Things (IoT) sensor nodes, wearable devices, and implantable biomedical systems.

Creation of self-concealing PUFs using innovative immersed-in-logic design

The PUFs invented by the researchers often demonstrate the first-of-its-kind capacity to be completely submerged and concealed in the digital logic that they actually defend. This is facilitated by the largely digital nature of the PUF architecture, which enables the location, routing, and alignment of digital standard cells, equivalent to traditional digital circuits. This decreases production costs as traditional digital automated design methodologies assisted by commercial software design tools can be extended to the design of the PUF.

In addition, the PUF digital architecture enables the generation of secret keys to be interspersed within the same logic that uses such keys as cryptographic data security units and encrypted data handling microprocessors. The immersed-in-logic method disperses the PUF standard cells among the cells used for digital logic, thus “hiding” or concealing any overt points of attack for hackers attempting to recover unique chip signals to physically recreate the keys.

This ability to self-conceal raises the attack initiative by about 100 times. It also increases the expense of targeting typical chips to millions of dollars with state-of-the-art equipment, relative to tens of thousands of traditional stand-alone PUFs.

Next steps

The NUS research team will continue to look at the integration of computer architecture, physical security, and deep learning in order to create next-generation stable chips systems. This technical advancement is motivated by the growing need for privacy and information protection, with the increasingly widespread implementation of chips systems that make sense of and process personal and confidential information.

The team is also seeking universal and ultra-low-cost hardware security capabilities by close physical integration of architectures and security primitives with circuitry that is commonly accessible on any chip device, ranging from logic, memory, intra-chip data connectivity, and accelerators. At the end of the day, the team’s latest advance is supposed to allow hardware security at the granularity of any silicon chip, including within individual chip subsystems.

However, PUFs do face problems in terms of stability and periodic misidentification of fingerprints. Researchers’ PUFs solve these problems with a novel technique in which on-chip sensors and machine learning algorithms are used to anticipate and detect PUF instability, as well as to make necessary changes to produce higher protection and stability PUF performance. Unusual ambient factors such as temperature, voltage, and noise, which are also used in physical attacks, may be monitored using this technique.